應屆畢業(yè)生
學歷不限
2025-05-05 08:50:00
1079人關(guān)注
職位描述
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崗位職責:
1. Physical implementation of advanced technology chips.
2. Design methodology development and innovation for advanced technology challenges.
3. Be responsible for 22/16/12/10/7/5nm chip implementation for customer’s projects or internal system test chips.
4. Be responsible for advanced node PPA benchmark, and solution development.
5. EDA tool new features enablement.
6. Customer onsite/offsite supports will be required on demand.
任職要求:
1. MS or above in EE, CS related fields. Experience in APR, physical verification, chip implementation, or CAD development is plus.
2. New graduate or 3 years working experience in chip physical implementation.
3. Familiar with Synopsys/Cadence APR tools/flows.
4. Familiar with TCL/Perl/Python programming.
5. Experience with TSMC advanced technology is plus.
6. Proven record in production tape-outs is plus.
1. Physical implementation of advanced technology chips.
2. Design methodology development and innovation for advanced technology challenges.
3. Be responsible for 22/16/12/10/7/5nm chip implementation for customer’s projects or internal system test chips.
4. Be responsible for advanced node PPA benchmark, and solution development.
5. EDA tool new features enablement.
6. Customer onsite/offsite supports will be required on demand.
任職要求:
1. MS or above in EE, CS related fields. Experience in APR, physical verification, chip implementation, or CAD development is plus.
2. New graduate or 3 years working experience in chip physical implementation.
3. Familiar with Synopsys/Cadence APR tools/flows.
4. Familiar with TCL/Perl/Python programming.
5. Experience with TSMC advanced technology is plus.
6. Proven record in production tape-outs is plus.
注：聯(lián)系我時，請說是在淮安經(jīng)濟技術(shù)開發(fā)區(qū)人才網(wǎng)上看到的。
工作地點
地址：宜昌伍家崗區(qū)九龍湖國際企業(yè)總部
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