應屆畢業生
學歷不限
2025-04-24 00:02:28
2896人關注
職位描述
該職位還未進行加V認證，請仔細了解后再進行投遞！
職責描述:
1.RTL synthesis, SDC/UPF verification, low power design implementation for advanced technology chips.
2.Design flow/methodology development and innovation for front-end design challenges.
3.Be responsible for RTL verification, synthesis, low power design, and STA/timing closure works for customer’s projects and internal system test chips.
任職要求:
1.MS or above in EE, CS related fields. Experience in Digital IC design flow (from Synthesis, DFT, MBIST, Formality, STA), RTL design, RTL verification is plus.
2.New graduate or 3 years working experience.
3.Familiar with EE CAD tool such as Design compiler, DFT complier, MBIST, n-Lint, Verdi, Verilog tools/flows.
4.Familiar with tcl/Perl/Python program.
招聘人數：1人
注：聯系我時，請說是在淮安經濟技術開發區人才網上看到的。
工作地點
地址：南京江寧區南京-江寧區九龍湖
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